The invention relates to analog/digital converters (ADC) with a high conversion frequency and more particularly to ADC usable in the video field.
One already knows so-called "flash" ADC which comprise a voltage divider constituted for example by a resistive array supplying 2.sup.N stepped reference voltages. In order to convert an analog signal into an N-bits word, they include 2.sup.N comparators, each of which compares the analog signal with one of the reference voltages. The comparator outputs are connected to a coding device designed to supply the N bits of the logic word. All comparators are controlled in parallel at each clock cycle and the conversion frequency is equal to the clock frequency. However, such a number of comparators occupies a substantial circuit surface and is power consuming.
In order to reduce the number of comparators, so-called "half-flash" comparators have been provided. Analog signals are converted into logic words constituted by P high order bits and Q low order bits (P+Q=N). "Half-flash" converters comprise 2.sup.P comparators called high weight comparators for supplying after coding, during a first clock period, high order bits, and 2.sup.Q comparators called low weight comparators for supplying after coding, during the next clock period, low order bits.
But such "half-flash" comparators have a conversion frequency half that of "flash" converters. Moreover, they must include means for maintaining the analog input voltage during two clock periods as for example sample and hold circuits.